EDN

Power tool taps clock gating

Claiming breakthrough technology in IC power optimization, Calypto Design Systems Inc. (Santa Clara, Calif.) this week will announce PowerPro CG, a tool that automatically adds clock-gating logic to ...
Electronic Design

Sequential Power Optimization Tool Pinpoints Clock-Gating Opportunities At RTL

Unlike combinational power reduction tools, PowerPro CG identifies and generates sequential clock-gating transformations. It fits into existing design flows with industry-standard library, timing, and ...
EDN

Circuit simulation tool simplifies clock designs

Norwood, Mass. — Analog Devices Inc. claims engineers can now create complete, robust timing solutions in minutes with its ADIsimCLK clock IC design and simulation tool and three new clock ICs. The ...
Embedded

FPGA Clock Schemes

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.